A: Palo Alto, California, United States
On December 1, 1957, on pages 3-4 of his manuscript patent notebook for Fairchild Semiconductor in Palo Alto, California, physicist Jean Hoerni recorded a "Method of protecting exposed p-n junctions at the surface of silicon transistors by oxide masking techniques." This was his first expression of the planar process, a radically new transistor design in which the oxide layer is left in place on the silicon wafer to protect the sensitive p-n junctions underneath. Focused on getting its first semiconductor devices into production, Fairchild Semiconductor did not pursue Hoerni’s planar approach at that time.
Due to concerns about possible contaminants, conventional wisdom required removing the oxide layer after completion of oxide masking, thus exposing the junctions. Hoerni viewed the oxide instead as a possible solution - his "planar" approach, named after the flat topography of the finished device, would protect these junctions, and two years later it would become an essential element in the manufacturing of Robert Noyce’s 1959 invention of the first commercially manufactured monolithic integrated circuit, the basis for virtually all semiconductor manufacturing today. Therefore Hoerni did not write a patent disclosure for what would become U.S. patent 3025589 until January 1959.
Hoerni, J. A., "Method of Manufacturing Semiconductor Devices," U. S. Patent 3,025,589 (Filed May 1, 1959. Issued March 20, 1962). See also Hoerni’s U.S. Patent No. 3,064,167.
Hoerni, J. A., "Planar Silicon Diodes and Transistors," paper presented at the 1960 Electron Devices Meeting, Washington, D. C. - October 1960 reprinted as Fairchild Semiconductor Technical Paper TP-14. (1961).